A divider unit generator

Romain Michard, Arnaud Tisserand and Nicolas Veyrat-Charvillon

Arénaire team, LIP

NEW: divgen-0.11 released on 2005-11-23!


Divgen is a tool that generates efficient division hardware units for both ASIC and FPGA targets. It produces synthesizable VHDL descriptions of optimized division units for various algorithms and parameters.

The supported algorithms are: restoring algorithm, non-restoring algorithm and SRT algorithms.

The main parameters supported by divgen are: operands widths, radix of the quotient digits (powers of 2), quotient digit set for a given radix (e.g. redundancy level), representation system of the residual (e.g. redundant number systems for ASIC or 2's complement for FPGA), rounding scheme, saturation, pipelining, loop unrolling, control signal


computer arithmetic, division, SRT, circuit generator, ASIC, FPGA.

Version 0.11:

Version 0.1:

Development page:

divgen project