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2 projet(s) trouvé(s).
1. Divgen - Divgen is a divider generator. It generates synthesizable VHDL descriptions of division units. Various algorithms, representations, radices, and parameters are supported.
 
  • Development Status: 4 - Beta [Filter]
  • Environment: Console (Text Based) (Now Filtering)
  • Intended Audience: Developers (Now Filtering) , End Users/Desktop [Filter]
  • License: GNU General Public License \(GPL\) [Filter]
  • LIP research teams: Arénaire \(computer arithmetic\) (Now Filtering)
  • Natural Language: English (Now Filtering)
  • Operating System: Linux [Filter]
  • Programming Language: C++ (Now Filtering)
  • Topic: Electronic Design Automation (EDA) [Filter]
Activity Percentile: 0.00
Activity Ranking: 0.00
Register Date: 31/08/2004 11:18

2. Higher-Order Table-Based method - VHDL generator for function evaluation operators using the Higher-Order Table-Based Method (HOTBM).
 
  • Development Status: 4 - Beta [Filter]
  • Environment: Console (Text Based) (Now Filtering)
  • Intended Audience: Developers (Now Filtering)
  • License: GNU General Public License \(GPL\) [Filter]
  • LIP research teams: Arénaire \(computer arithmetic\) (Now Filtering)
  • Natural Language: English (Now Filtering)
  • Operating System: Linux [Filter]
  • Programming Language: C++ (Now Filtering)
  • Topic: Electronic Design Automation (EDA) [Filter]
Activity Percentile: 0.00
Activity Ranking: 0.00
Register Date: 04/03/2005 12:55

 

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